1. Field of the Invention
The present invention relates to a metal-oxide semiconductor field-effect transistor structure, and particualy to the drain structure of such semiconductor device. Also, the present invention relates to a method of making metal-oxide semiconductor field-effect transistors.
2. Description of the Prior Art
As is well known, the lightly doped drain structure of a metal-oxide semiconductor field effect transistor (abbreviated MOSFET) comprises a lightly doped section starting from a location under one edge of the gate and extending a relatively short distance apart from said location, and a heavily doped section following said lightly doped section and extending a relatively long distance apart from the gate. The presence of such lightly doped section ahead of the heavily doped section will cause the strength of the electric field appearing in the vicinity of the drain of the device to be reduced so as to suppress appearance of hot carriers. Such hot carriers are liable to invade the gate through the underlying metal oxide and to remain in the gate, and as a result the performance of the device will change with age. Adoption of the lightly doped drain structure in a MOSFET improves substantially the reliability of the device.
The lightly doped section, however, functions as a parasitic resistor, and disadvantageously it will lower the current driving capability of the device. In an attempt to solve this problem a profiled lightly doped drain structure (abbreviated PLDD) was proposed (See the paper "Profiled Lightly Doped Drain (PLDD) Structure for High Reliable NMOSFETs", Y. Toyoshima et al, Digest of Techical Papers, Symposium on VLSI Technology, pp.118-119, 1985). FIG. 1 shows, in section, a PLDD structure. It comprises a P-type silicon substrate 100, a gate insulating layer 101 formed on the top surface of the substrate 100, a gate 103 built on the gate insulating layer 101, an N-type source diffusion layer 108a, and an N-type drain diffusion layer 108b. The gate 103 has a surrounding wall 105, and the source and drain diffusion layers 108a and 108b have electrodes 109 and 110 respectively. These electrodes 109 and 110 are embedded in an overlying insulating layer 111. It is noted that: the drain diffusion layer is composed of an upper short projection 107 of least concentration of impurity such as arsenic, a surrounding section 104 of less concentration of impurity such as phosphorus, and an elongated section 108b of relatively high concentration of impurity such as arsenic, lying contiguous to the upper projection 107 and surrounding section 104, which end at a location under one edge of the gate 103.
The coexistence of less doped core 107 and least doped enclosure 104 prevents effectively the lowering of the current driving capability of the device.
In the PLDD structure, however, carriers are liable to come together toward the upper surface of the substrate 100, and as the device size is decreased, hot carriers will be most likely to appear in the vicinity of the upper surface of the substrate 100, invading the gate 103 through the underlying insulating layer 101 to lower the characteristics of the devive. Also, further miniaturization of MOSFETs having a PLDD incorporated therein will cause the least doped enclosure 104 to function as a parasitic resistor, thereby lowering the current driving capability of the device.